Low-power Variable-length Fast Fourier Transform Processor
Journal
IEE Proceedings Computers & Digital Techniques
Journal Volume
152
Journal Issue
4
Pages
499-506
Date Issued
2005-07
Author(s)
Abstract
Fast Fourier transform (FFT) processing is one of the key procedures in the popular orthogonal frequency division multiplexing (OFDM) communication systems. Structured pipeline architectures and low power consumption are the main concerns for its VLSI implementation. In the paper, the authors report a variable-length FFT processor design that is based on a radix-2/4/8 algorithm and a single-path delay feedback architecture. The processor can be used in various OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T), asymmetric digital subscriber loop (ADSL) and very-high-speed digital subscriber loop (VDSL). To reduce power consumption and chip area, special current-mode SRAMs are adopted to replace shift registers in the delay lines. In addition, techniques including complex multipliers containing three real multiplications, and reduced sine/cosine tables are adopted. The chip is fabricated using a 0.35 μm CMOS process and it measures 3900 μm × 5500 μm. According to the measured results, the 2048-point FFT operation can function correctly up to 45 MHz with a 3.3 V supply voltage and power consumption of 640 mW. In low-power operation, when the supply voltage is scaled down to 2.3 V, the processor consumes 176 mW when it runs at 17.8 MHz. © IEE, 2005.
SDGs
Other Subjects
Feedback architecture; Fourier transform processor; OFDM-based communication systems; Semiconductor processing technology; Computer architecture; Digital signal processing; Electric currents; Electric potential; Energy utilization; Fourier transforms; Orthogonal frequency division multiplexing; Static random access storage; VLSI circuits; Program processors
Type
journal article