A 20-Gb/s 1: 2 demultiplexer with capacitive-splitting current-mode-logic latches
Journal
IEEE Transactions on Microwave Theory and Techniques
Journal Volume
55
Journal Issue
8
Pages
1624-1632
Date Issued
2007
Author(s)
Abstract
This paper presents a high-speed 1:2 demultiplexer (DEMUX) implemented in a 0.18-mum CMOS process. By employing a capacitive-splitting architecture for the current-mode-logic latches, a significant speed improvement is achieved in the proposed DEMUX. Provided a 2 23 - 1 pseudorandom bit sequence from the pattern generator, the fabricated circuit operates at an input data rate up to 20 Gb/s. The fully integrated DEMUX consumes a dc power of 150 mW from a 2-V supply voltage.
SDGs
Type
journal article