Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding
Resource
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Journal
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Journal Volume
2
Pages
193 - 196
Date Issued
2001
Author(s)
Abstract
This paper presents a hardware-efficient architecture of tree-depth scanning (TDS) and multiple-quantization (MQ) scheme for MPEC-4 still texture coding. By means of the novel architecture, the TDS can achieve its maximal throughput to area ratio and minimal external memory access with only one wavelet-tree size on-chip memory. Besides, MQ adopts the proposed POT (power of 2) quantization, which is proved to have very similar performance to generic (user-defined coefficients) scalar quantization, to achieve the most cost-effective hardware implementation. The prototyping chip has been implemented in a TSMC 0.35 /spl mu/m CMOS technology. This architecture can handle 30 4-CIF frames per second with 5 spatial layers and 3 SNR layers scalability at 100 MHz clock frequency. © 2001 IEEE.
Event(s)
2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Other Subjects
Architecture designs; External memory access; Frames per seconds; Hardware implementations; Maximal throughput; Multiple quantizations; Novel architecture; Scalar quantization; CMOS integrated circuits; Forestry; Motion Picture Experts Group standards; Image compression; Microprocessor chips; Scanning; Signal to noise ratio; Software prototyping; Vector quantization; Hardware; Image coding; Multiple quantization (MQ); Tree depth scanning (TDS)
Type
conference paper
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