A Wide-Range and Fast-Locking All-Digital Delay-Locked Loop Using a Phase-Tracing Delay Unit
Date Issued
2011
Date
2011
Author(s)
Chen, Liang-Hsin
Abstract
Nowadays, system-level integration has become the main trend in the IC design fields. DLLs are widely used in SoCs for solving the clock skew issues and synchronizing each intellectual property (IP) and module. However, wide-range analog DLLs which could be designed as an IP are becoming harder to be implemented and more difficult to be designed in the advanced processes nowadays. In contrast, the all-digital DLLs (ADDLLs) are easier to be realized and integrated with the digital systems in these advanced processes. A wide-range and fast-locking ADDLL as an IP for the system-level is proposed in this work.
In this thesis, a novel phase-tracing delay unit (PTDU) will be proposed as well. The purpose of using a PTDU is to replace with the long delay line which is used in wide-range DLLs and to enlarge the operating frequency range which is over 6.7MHz-1.24GHz. Moreover, the PTDU and the CSD-based control unit achieve fast-locking time which is only 5 cycles. The FSMs and TDC-based code generators provide low jitter performance, which is 2.22ps at 1.24GHz in our measurement. The chip was fabricated in TSMC 90nm CMOS process and occupied 0.0318mm2 active area.
Subjects
All-Digital Delay-Locked Loop (ADDLL)
Wide-Range
Fast-Locking
Clock-Synchronized Delay (CSD)
Time-to-Digital Converter (TDC)
Type
thesis
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