Architecture and Algorithm Design of High-resolution Real-time Video Object Segmentation
Date Issued
2009
Date
2009
Author(s)
Liang, Chia-Cheun
Abstract
Video Segmentation has been widely used in video coding, virtual communication, image / video special effect processing, and intelligent surveillance systems. Video segmentation separates a video frame into meaningful binary masks. After post-processing, these masks can represent objects in a video. Then the data can be used by object tracking or behavior analysis algorithms to further analyze the video content according to object characteristics, realizing modern intelligent video analysis systems. Related applications include intelligent video surveillance systems, automatic home caring systems, and public place safety alarm systems.As intelligent video analysis technique evolves, the goal of advanced systems turns to fully-automatic systems which can handle enlarged coverage and resolution with faster frame-per-second (fps) rates. In addition, to alleviate the computation load of the central server of a system and to attain efficient system bandwidth usage, part of the computation should be handled at terminal side, i.e., at camera side. The computed data are then transmitted to central server occupying less bandwidth. Since video segmentation leaves binary masks instead of the entire image frame, putting video segmentation at terminal side greatly reduces the amount of transmission. Furthermore, the high compatibility between video segmentation algorithms ensures implementation integrity. It is acknowledged that video segmentation can be integrated into camera devices.In this thesis, a run-processing method which accelerates multiple functions widely used in video segmentation algorithms is proposed to support real-time high-resolution video object segmentation algorithms. Instead of using conventional pixel-based solutions, the presented method utilizes run-coding to reduce redundant computation and at the same time lower system bandwidth requirements.The proposed method is carefully designed to ensure a practical hardware implementation. The corresponding hardware architecture is introduced and fabricated as a single-chip solution. This architecture possesses a two-phase partial-data reuse scheme. Moreover, corresponding storage format is adopted for certain functions, thus further diminishing overall system bandwidth. The chip implementation can be integrated into camera devices and serves as a terminal-device accelerator in next-generation intelligent video analysis systems.
Subjects
video segmentation
hardware implementation
image processing
rectangular binary morphology
connected component labeling
Type
thesis
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