Suppression of short channel effects in ferroelectric Si junctionless transistors with a sub-10 nm gate length defined by helium ion beam lithography
Journal
Journal of Materials Chemistry C
Journal Volume
9
Journal Issue
26
Pages
8285-8293
Date Issued
2021
Author(s)
Abstract
The performance enhancements of Si junctionless transistors (JLTs) with a short gate length (LG) below 10 nm by a pronounced ferroelectric (FE) gate dielectric were demonstrated for the first time. A TiN gate withLG= ~8 nm was defined by helium ion beam lithography (HIBL) using hydrogen silsesquioxane as a resist. As compared with the paraelectric HfO2gate oxide, the FE Hf0.5Zr0.5O2gate dielectric leads to a suppression of the off-state current (IOFF) by ~2 orders of magnitude and a reduction of the minimum subthreshold swing (SS) to~33 mV dec-1, along with an enhancement of the on/off ratio in the reverse-sweep direction in JLTs withLG= ~8 nm. JLTs with a longLG= 5 ?m were also investigated for comparison, revealing a decrease ofIOFFby ~25× and the sub-60 mV dec-1SS across ~3 orders of drain current (ID) under a large drain voltage (VD= 0.5 V) operation during the reverse sweep in FE JLTs. A time domain analysis indicated that the transient negative capacitance (TNC) effect takes place in the FE gate dielectric. A physical model was proposed to account for the TNC effect and the sub-60 mV dec-1SS based on the capacitance increase during the FE polarization switching. This study also demonstrates for the first time the fabrication of nanoelectronic devices with a sub-10 nm critical dimension by using the HIBL technique with a damage-free dose. ? The Royal Society of Chemistry 2021.
Subjects
Capacitance
Drain current
Ferroelectricity
Gate dielectrics
Helium
Ion beams
Ions
Silicon
Titanium nitride
Hydrogen silsesquioxane
Junctionless transistors
Nanoelectronic devices
Negative capacitance
Performance enhancements
Polarization switching
Short-channel effect
Sub-threshold swing(ss)
Time domain analysis
Type
journal article