Using Linear Models to Evaluate the Performance of Flash AD C's BIST under Process Variation
Date Issued
2005
Date
2005
Author(s)
Lai, Kuan-Ting
DOI
en-US
Abstract
As today’s IC technology continues moving forward nanometer era, the cost of using external testers to distinguish between faulty and good circuits has risen to an unacceptable high level. Therefore, DfT (Design-for-Test) techniques have prevailed in recent years. However, unlike their digital counterparts, the Analog DfT techniques are far from being widely adopted. The main reasons are (1) lack of reliable method to evaluate DfT techniques, and (2) the time-consuming simulation process. Besides, the BIST (Built-in Self Test) circuit suffers the same process variation effects as its DUT (Device under Test) circuit. This fact makes evaluating BIST performance more difficult.
In this thesis, we propose a method to evaluate BIST performance under process variation. The correlations between process parameters are considered, and simulation result is more close to real life. An automation evaluation tool is implemented, and a 6-bit flash ADC with a static ramp BIST is utilized as testing vehicle. We also introduce a novel methodology for accelerating the evaluation process of flash ADC. The experimental result shows that the new method is about hundred times faster than the Monte Carlo method.
Subjects
線性模型
快閃式類比數位轉換器
內建自我測試器
製程變異
Linear Model
Flash ADC
BIST
Process Variation
Type
thesis
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