A 98.6μW acoustic signal processor for fully-implantable cochlear implants
Journal
2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Date Issued
2016
Author(s)
Abstract
This paper presents a low-power acoustic signal processor for fully-implantable cochlear implants. The developed processor supports adaptive beamforming, frequency-domain analysis, envelope detection, channel combination, and magnitude compression. Power and area are minimized by leveraging dedicated real-valued FFT, register count minimization, data allocation optimization, hardware complexity reduction, and minimum-energy-point operation. Compared to complex-valued FFT, real-valued FFT achieves 44.36% power reduction. Register count minimization and data allocation for FFT output reordering yields 28.07% and 27.09% area and power reduction, respectively. Envelope detection and log-compression are realized by hardware-efficient CORDIC engines. The processor is scalable to support various numbers of channels. This chip is implemented in 90-nm CMOS and the core area is 0.47 mm 2 . It dissipates 98.6 μW at 50 kHz, 0.33 V for a latency of 3 ms.
SDGs
Type
conference paper