Research of Watt-Level High Power Density Transformer Combined LDMOS Power Amplifier for Wireless Communication
Date Issued
2016
Date
2016
Author(s)
Chang, Tien-Tzu
Abstract
With the evolution of semiconductor process and development of wireless communication system, implementing radio frequency integrated circuit with CMOS becomes the focus point of industry market. In the transceiver design, power amplifier is the most critical and significant component. This thesis emphasizes the design and analysis of laterally diffused metal oxide semiconductor (LDMOS). Due to the high supply voltage, two LDMOS power amplifiers in 40-nm process are designed and analyzed separately. The first power amplifier design achieves high power area density to reduce the chip area and cost effective. In order to target the demand of high data rate and long distance, the second power amplifier design obtains a watt-level high output power that becomes high output power performance in 3.5-GHz band that is in CMOS process to raise circuit integrity and reduce cost. In chapter 3, a compact 3.5-GHz transformer combined power amplifier with LDMOS transistors is designed in 40-nm CMOS process. This frequency band can be applied in 4G/LTE mobile devices, where has 80MHz bandwidth for uploading from 3410MHz to 3490MHz with the central frequency of 3450MHz. LDMOS is usually used in the design of RF power amplifiers in the base station since the high breakdown voltage provides high output power. In order to reduce the chip size, the power cells of power amplifier use transformer to do power combining, impedance matching and single-to-differential ended simultaneously. Larger device selection will bring larger gate-to-drain capacitance and it will make power amplifier instable. The neutralization capacitor can degrade the gate-to-drain capacitance, and effectively increase the stability and gain for power amplifier design. This power amplifier is the highest power density about the frequency bands in the recent power amplifiers of CMOS process. The output power can reach the highest performance as 26.5 dBm with only 0.259 mm2, and achieves in the highest power area density of saturated output power as 1724 mW/mm2 and the highest power area density of OP1dB as 992.4 mW/mm2. In chapter 4, a 3.5-GHz watt-level transformer combined power amplifier with 3-D architecture implements in 40-nm CMOS process. For watt-level output power design, 4-ways power combining is realized by the shortest path for the radial power combiner and longer path for the radial power splitter. The long path of input splitter can also reduce the impedance transform ratio of input matching network. By sharing the same area vertically in 3-D architecture, the occupied area of radial power combiner and power splitter can be minimized significantly. This technique breaks the bottle neck of the conventional 2-D power-combined techniques that achieves the symmetry of circuit layout and flexibility of impedance transformation without compromising and limiting in various conditions of different frequency bands. This watt-level 3-D architecture transformer-combined power amplifier achieves the highest output power in CMOS process among the recent published 3.5-GHz band power amplifiers. The maximum output power can be achieved in 31.26 dBm of high output power performance.
Subjects
Power amplifier
LDMOS
Transformer combining
High power
High operating voltage
High power area density
40-nm CMOS process
Type
thesis
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