Digital Error-Averaging Technique for Pipelined Analog-to-Digital Converter
Date Issued
2004
Date
2004
Author(s)
Huang, Wei-Jen
DOI
zh-TW
Abstract
The pipeline architecture is more suitable for some applications with the requirement of high resolution than the flash analog-to-digital converter (ADC) architectures, due to its small size and low power consumption. However, the accuracy of a pipelined ADC architecture is susceptible to circuits imperfections, such as offset voltages, gain errors, non-linearity of operational trans-conductance amplifier (OTA) and capacitors mismatch and so on. The effect of circuit impairment is associated with each stage of a pipelined ADC architecture. The disadvantage of non-linearity still remains limited on component mismatch. To date, some techniques have been proposed for improving the INL. These techniques used some extra analog circuits or calibration circuits for the implementation of a pipelined ADC. In this thesis, we present a new digital error-averaging technique to reduce the mismatch effect due to the employed components.
In this research, a 12-bit 50MS/s pipelined ADC with a digital error-averaging technique has been designed and implemented with standard 0.35-µm double-poly four-metal CMOS process. This technique used two pass commutating feedback-capacitors at one sample input signal, and used digital circuits to average the twice data for improving the integral non-linearity of pipelined ADC.
Subjects
類比數位轉換器
analog-to-digital converter
Type
thesis
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