Graceful Register Clustering and Rebanking for Power and Timing Balancing
Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Start Page
1
End Page
1
ISSN
0278-0070
1937-4151
Date Issued
2024
Author(s)
Abstract
As dynamic power has become the bottleneck to achieving low power, clock power reduction is crucial in modern IC design. Register clustering can effectively save clock power because of significantly reducing the number of clock sinks and register pin capacitance, clock routed wirelength, and the number of clock buffers. In this article, we propose effective mean shift to naturally form clusters according to register distribution without placement disruption. Effective mean shift fulfills the requirements to be a good register clustering algorithm because it needs no prespecified number of clusters, is insensitive to initializations, is robust to outliers, is tolerant of various register distributions, is efficient and scalable, and balances clock power reduction against timing degradation. Furthermore, we devise a rebanking mechanism to legalize the clustering result according to the adopted multibit register library. Experimental results show that our approach achieves superior power and timing balancing.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article