Capacitance Behavior of Nanometer FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Gate Tunneling Leakage Current
Journal
MIEL
Pages
61-66
Date Issued
2006-05
Author(s)
Abstract
This paper reports the CSG/CDG capacitance behavior of 100 nm fully-depleted (FD) SOI CMOS devices with HfO2 high-k gate dielectric considering gate tunneling leakage current. According to the 2D simulation results, a unique two-step CSG/CDG versus VG curve exists for the device with the 1.5nm HfO2 gate dielectric due to the vertical displacement effect. Gate tunneling leakage current has a more impact on CDG as compared to CSG. © 2006 IEEE.
SDGs
Type
conference paper