VLSI implementation of visual block pattern truncation coding

Journal
IEEE Transactions on Consumer Electronics
Journal Volume
44
Journal Issue
3
Pages
490-499
Date Issued
1998
Author(s)
Liu, Y.-C.
Lai, Y.-K.
Tsai, T.-H.
Wu, P.-C.
Chen, L.-G.
DOI
URI
Abstract
The paper proposes a pipelined architecture of a visual block pattern truncation coding algorithm to minimize the mean square error. Using this chip, the VBPTC based system can be applied to real-time encoding for moving pictures.
Type
journal article

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