An NoC Router Design with Built-In Self-Test and Fault Tolerance Mechanism
Date Issued
2011
Date
2011
Author(s)
Li, Chien-Hsing
Abstract
Network-on-Chips (NoCs) is a promising interconnect architecture for in System-on-Chips (SoCs) because it exhibits better scalability than the traditional bus architecture. However, NoCs also bring new challenges to manufacturing testing one of which being the limited test access to embedded cores.
In this thesis, we propose a built-in self-test (BIST) and fault-tolerance technique for the NoC routers. The proposed BIST scheme covers the FIFO’s and the data path between the FIFO’s of adjacent routers because these components occupy most of the router area. Highly parallelized, the BIST procedure consumes very short test time. A diagnosis module analyzes the BIST results to determine the fault location. If the fault resides in the FIFO’s, the fault tolerance mechanism will be activated so that the faulty register is skipped. For faults that affect one, several, or all input/output channels of a router, one can adopt adaptive routing algorithm to get around the faulty channels or routers.
An NoC based on [5] was implemented to validate the proposed techniques. Simulation results show high fault coverage (for stuck-at and transition faults) and high diagnosis resolution with acceptable area overhead.
Subjects
Network-on-Chips
Built-in Self-Tet
Fault Tolerance
Type
thesis
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