Low Power Analog Signal Processor for Bio-Medical Applications
Date Issued
2009
Date
2009
Author(s)
Pang, Wen-Yi
Abstract
The application of VLSI technology in bio-medical instrumentation enables the emerging of the bio-MEMS and wireless technologies. By combining these technologies, personal remote sensing has become a popular research area. It applies an implantable bio-medical circuit for neural stimulation and uses RF signal to transmit recorded physiological signals. In such implanted bio-medical circuits, low power operation is very important because the heat spread caused by the implanted circuit will increase local temperature which may damage organs and neurons. This thesis presents a signal processor with area-efficient DC offset cancellation. For this processor, this work designs the building blocks of a low power 10-bit successive-approximation-register analog-to-digital converter (SAR ADC) and a low power decimation filter for bio-medical applications.n the 10-bit SAR ADC, an energy-saving capacitor array and a splitting comparator architecture is proposed to achieve low power consumption. The average switching energy of the capacitor array can be reduced by 68% compared to a conventional architecture. The splitting comparator consists of two gain paths, through which power saving for an A/D conversion is achieved by selecting the appropriate comparison path and disabling the unused path. The measured signal-to-noise-and-distortion ratio of the ADC is 58.4 dB at 500KS/s sampling rate with power consumption of 42μW from a 1-V supply. The ADC is fabricated in a 0.18-μm CMOS technology. low-power decimation filter for portable electrocardiogram (ECG) monitoring applications is also presented. This decimation filter consists of two parts: front-end and back-end. The font-end filters noise to regain ECG signal while the back-end computes the direct current (DC) offset caused by the local oscillator (LO) leakage and subtracts it from the input. This makes the ECG signal stays within the allowable ADC input range. In addition, selecting the right decimation factors gives the most efficient design in terms of storage requirements and the number of multiplications per second (MPS). Finally, the functionality of the decimation filter is tested and verified with an Altera Stradix EP1S80 FPGA board and Tektronix TLA 715.
Subjects
SAR ADC
Decimation filter
Type
thesis
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