A 100GHz phase-locked loop in 0.13μm SiGe BiCMOS process
Journal
Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Date Issued
2011
Author(s)
簡俊超
Abstract
A fully integrated 100GHz phase-locked loop (PLL) is demonstrated in 0.13μm SiGe BiCMOS process. The PLL employs a fundamental-frequency differential Colpitts voltage-controlled oscillator (VCO) with 8.3% tuning range, which achieves a phase noise of -124.5dBc/Hz at 10MHz offset, and a single-ended output power of 3dBm. The FoM of this VCO is the best among 90-100GHz VCOs. A Miller divider, operating from 50GHz up to 130GHz, is designed and the Gilbert-mixer phase detector is used to attenuate reference spurs. The total lock range of the PLL is from 92.7 to 100.2GHz, the phase noise is -102dBc/Hz at 1MHz offset, and reference spurs are not observable. The PLL dissipates 570mW and occupies 1.21mm 2 .
SDGs
Type
conference paper