Research on Interconnect Analysis and Floorplanning for SOC
Date Issued
2002-07-31
Date
2002-07-31
Author(s)
DOI
902215E002009
Abstract
In general, optimizing IC performane
needs to reduce the interconnect delay as
much as possible. To achieve this goal,
buffers are added in a long net to reduce its
delay value. In this work, we try to solve the
multi-net routing and buffer insertion problem
by a new method. Instead of dividing the
problem into different stages, our method
tries to route and insert buffers
simultaneously. Our method also considers
net congestion constraint, buffer congestion
constraint and delay target of each net as our
algorithm constraints, which have not been
considered in all previous works. Thus, we
have developed a global router combined with
buffer-insertion for SoC design automation.
The global router includes a Manhattan
Routing (MR) algorithm and a Maze-based
Between-buffer Routing (MBR) algorithm,
where the processing speed of MR is quite
fast that it can be integrated into the iterative
floorplanning algorithm to promote the
routability of a floorplan solution.
Subjects
晶片系統
平面規劃
緩衝器
全
域繞線器
域繞線器
Publisher
臺北市：國立臺灣大學電機工程學系暨研究所
Type
report
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