A hardware evaluation of memory address translation for mobile virtualization
Journal
Proceedings - 2014 International Conference on Information Science, Electronics and Electrical Engineering, ISEEE 2014
Journal Volume
2
Pages
992-996
Date Issued
2014
Author(s)
Lee, Y.-C.
Abstract
The computing power of mobile devices has grown significantly in recent days. People begin bringing as many applications as possible to these devices. Virtualization is exactly one of these examples. However, we found most of the research on mobile virtualization lacks an appropriate evaluation at the hardware level. In this paper, we would like to study the performance of oPT, a newly proposed mechanism of memory management for mobile virtualization, at the hardware level with a comparison to the most common mechanism. However, it is complicated and costly to integrate oPT into existing hardware architectures. We instead present a simple yet efficient method based on FPGAs to verify the feasibility of oPT and evaluate its performance with several metrics. The results suggest that the hardware component adopted in oPT can operate at a frequency up to 2.3 times faster than the one in the original mechanism. When running at the same frequency, oPT can reduce the translation time by 64.7% with an increase of 2.5% in the resource usage of the FPGA. In addition to the measurement of the translation speed, the prototypes can further serve as the physical models for measuring power consumption.
Type
conference paper