Low Transmission Latency Method for 2D-mesh NoC Architecture
Date Issued
2007
Date
2007
Author(s)
Lee, Yen-Chang
Abstract
With the development of deep submicron chip technology, a chip can pack more than a billion transistors nowadays. This capacity will allow the System-on-Chip (SoC) designs with a large amount of IP cores on a single chip. However, the inter-communication between IP cores becomes a new challenge. In recent years, Network-on-Chip (NoC) has been proposed to provide an on-chip communication infrastructure with better scalability and reliability. The 2D mesh is a very popular topology of previous NoC designs, because of the simplicity with designing its routing algorithm and network scalability. However, mesh has a relatively large average distance between any two nodes; hence some long distance traffic suffers from high transmission latency. In this thesis, we proposed an easy design method for 2D mesh NoC, the concept is letting the long distance traffic traverse on an additional Level-2 mesh. Simulation results demonstrate that it can reduce the transmission latency of long distance traffic. The 2-level 12x12 mesh with 3x3 sub-meshes and 4x4 sub-meshes can reduce the minimum latency of Uniformly Distributed traffic by 32%, and 25% compared to normal mesh architectures, the area overhead of routers are 21.2%, and 11.9%, respectively.
Subjects
Network-on-Chip
System-on-Chip
mesh
2-level
Latency
Type
thesis
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