A fast analytical technique for estimating the bounds of on-chip clock wire inductance

Journal

Proceedings of the Custom Integrated Circuits Conference

Pages

241-244

Date Issued

2001

Author(s)

Lu, Y.-C.

Banerjee, K.

Celik, M.

Dutton, R.W.

DOI

10.1109/CICC.2001.929764

URI

https://scholars.lib.ntu.edu.tw/handle/123456789/502229

URL

https://www.scopus.com/inward/record.uri?eid=2-s2.0-0034835833&doi=10.1109%2fCICC.2001.929764&partnerID=40&md5=5a773c748819d6baff5155b746ab51ee

Type

journal article