Amplifier-Based Analog-to-Digital Converters Using Time-Domain Signal Processing
Date Issued
2015
Date
2015
Author(s)
Chen, Liang-Jen
Abstract
The amplifier-based analog-to-digital converter (ADCs), such as pipelined, cyclic, and two-step architecture, are a suitable candidate for sampling rates from a few mega samples per second (MSPS) up to 100MSPS or even above, and resolutions range from 8 bits to 16 bits. However, as CMOS technology continues to shrink, the decreased supply voltage would limit the swing of the ADC, and the reduced intrinsic gain of the transistors would make the conventional operational amplifier difficult to realize. Although the early proposed open-loop architectures with the analog/digital calibration can be implemented in an advanced CMOS process, the amplifier non-linearity issue would become more severe as CMOS technology continues to scale down. A sophisticated non-linear calibration would be required and complicates the design. In addition, as the voltage swing decreases, the resolution of the conventional voltage-domain ADCs are also limited as well. To solve the issue described above, a time-domain ADC (TADC) architecture is proposed in this thesis. Since the power consumption of the digital circuit decreases, and the resolution of a time-domain signal is improved with the technology scaling, the TADC becomes a candidate for the power efficient architecture in the advanced process. Also, since the time-domain signal range would not be limited by the decreased supply voltage, the non-linearity issue in the TADC architecture could be relieved. Two prototype ICs were designed during this research. In chapter 2, the first design is a 12-bit 3.4MS/s two-step cyclic TADC implemented in a 0.18um CMOS process. The proposed TADC uses a voltage-to-time converter (VTC) with a 12dB gain amplifier and the proposed time amplifier (TA) as residue amplifiers to achieve 12-bit resolution without high gain amplifiers. In addition, non-linear calibration, and the process variation tracking blocks are also not required. The noise analysis for each TADC building block is also presented in this chapter. To verify the noise analysis further, another TADC is fabricated with different devices sizes, in order to compare the measured signal-to-noise ratio (SNR) and signal-to-noise and distortion ratio (SNDR). In chapter 3, the second design is a 10-bit 40MS/s two-step TADC implemented in a 0.18um CMOS process. The second design is realized to improve the sampling rate of the first design, and also to eliminate the use of the amplifiers. Same as the first design, non-linear calibration, and the process variation tracking blocks are also not required. Since the TADC can operate without the non-linear calibration, the hardware complexity of the digital background calibration adopted in this work can be greatly reduced. Therefore, the calibration time of the TADC requires only 622 clock cycles, which is over 10 times less than prior voltage-domain digitally-calibrated ADCs.
Subjects
analog circuit design
analog-to-digital converter
digital calibration
noise analysis
Type
thesis