A CMOS Low Dropout Voltage Regulator with Full-Range Stability
Date Issued
2006
Date
2006
Author(s)
Huang, Chun-Hsiang
DOI
en-US
Abstract
Stability is the important issue during designing the LDO linear regulators. In the conventional architecture, the key factors affecting the stability are the variation of load current and the value of output capacitor. Therefore, there have been many proposed compensation methods to improve whole performance. According to the applications and output capacitor, the LDO linear regulators can be approximately classified into two groups: off-chip and on-chip output capacitor. These LDO linear regulators with off-chip capacitor have larger capacitance at output node and generate the dominant pole at low frequencies to achieve the stability. They are mostly used for the products with bigger system and area like TV. The other LDO linear regulators have smaller output capacitor, and thus the capacitor can be integrated into the chip, saving the total chip area. For the reason this kind of LDO linear regulators are well suited as a stable dc voltage supply for portable electronic devices.
This thesis proposes a LDO linear regulator stable for any output capacitor. By utilizing two techniques: capacitor multiplier and parallel power transistors a series pole-zero pairs are generated at frequencies to make the control loop has enough phase. The regulator is designed in a 0.18 μm 1P6M CMOS process. The post-layout simulation results verify the theoretical analysis and show that the regulator can be stable with any load capacitor. Besides, the DC gain is around 50 dB, and the maximum load current is 100mA.
Subjects
低壓降
穩壓器
全域穩定
CMOS
LDO
Regulator
Stability
Type
thesis
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