A 2×25 Gb/s clock and data recovery with background amplitude-locked loop
Journal
Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
Pages
281-284
Date Issued
2015
Author(s)
Abstract
A 2×25 Gb/s clock and data recovery circuit is fabricated in a 40-nm CMOS process. A background amplitude-locked loop is proposed to reduce the amplitude variation of a charge-steering-logic return-to-zero latch. The measured rms jitter is 2.26 ps and the peak-to-peak jitter is 15.56 ps for a 25 Gb/s PRBS of 2 7 -1. It dissipates 8.8 mw per channel from 1.15 V supply.
SDGs
Type
conference paper