Power-Supply-Noise-Aware Dynamic Timing Analyzer
Date Issued
2014
Date
2014
Author(s)
Hsieh, Hung-Yi
Abstract
Due to the effect of IR-drop and Ldi/dt, power supply noise can cause yield loss when testing VLSI chips. In this thesis, we propose a power-supply-noise-aware dynamic timing analyzer, IDEA (IR-Drop-aware Efficient timing Analyzer). The proposed analyzer provides reasonable accuracy at much faster speed than existing tools. This technique is very scalable because it is based on linear functions, instead of solving nonlinear functions. The experimental results show, for small circuits, the error is less than 1% compared with HSPICE. For large circuits, we achieved eight times speed up compared with NANOSIM. IDEA identifies 369 timing-violation test patterns (out of 31K test patterns) for a 1M gate benchmark circuit which are difficult to detect by traditional techniques.
Subjects
電源供應雜訊
電壓降
電感電壓
電荷
動態時序分析器
Type
thesis
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ntu-103-R01943142-1.pdf
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