Hardware accelerated aerial image simulation by FPGA
Journal
Proceedings - 2009 5th Southern Conference on Programmable Logic, SPL 2009
Pages
39-44
Date Issued
2009
Author(s)
Abstract
This paper describes a hardware implementation of aerial image simulation in lithography using FPGA. However, such simulators are presently performed using mainly software-based techniques on dedicated computers. The Hopkins partially coherent imaging equation is decomposed numerically by using singular value decomposition (SVD). The data input is a function which is consisting of rectangles as Manhattan geometry mask. For the convolution of mask functions with arbitrary kernels, a table lookup technique is used. For each single point intensity computation, it needs computation in the number of rectangles within a bounded window and the approximation order of the optical system adopted. This computation is done by FPGA on the order of O(R) instead of O(AmiddotR) which is the case in temporal machines. It is clearly shown how FPGA can be utilized efficiently to reduce the cost of computation.
Type
conference paper