An all-digital de-spreading clock generator
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
61
Journal Issue
1
Pages
16-20
Date Issued
2014-01
Author(s)
Abstract
An all-digital despreading clock generator (DSCG) is presented. For an input spread-spectrum clock with a modulation frequency of 15-40 kHz and a down spreading of 5000 ppm, this DSCG successfully realizes a nonspread-spectrum clock. It is fabricated in a 0.18-μm CMOS process. For an input spread-spectrum clock of 1.5 GHz with a down spreading of 5000 ppm and a modulation frequency of 30 kHz, the measured root-mean-square and peak-to-peak jitters of this DSCG are 2.94 and 22.78 ps, respectively. The active area including input/output buffers is 0.84 mm2. Its power consumption is 19.8 mW, for a supply of 1.8 V. © 2004-2012 IEEE.
Subjects
All-digital phase-locked loop (ADPLL); despreading; spread-spectrum clock
SDGs
Other Subjects
Electric clocks; Spectroscopy; All digital phase locked loop; Clock generator; CMOS processs; De-spreading; Modulation frequencies; Peak-to-peak; Root Mean Square; Spread spectrum clock; Frequency modulation
Type
journal article