Design on a Deserializer Circuit for the 10GBASE-LX4 Ethernet Receiver
Date Issued
2007
Date
2007
Author(s)
Cuei, Han-Wei
DOI
zh-TW
Abstract
With the fast proliferation and development of the Internet, the demand for high-speed communication networks has grown progressively. The bandwidth of local area network (LAN) already enters the generation of the 10 Gigabit Ethernet recently.
In the standard of IEEE 802.3ae, which is defined for the 10 Gigabit Ethernet, 10GBase-LX4 specification utilizes low-cost laser diodes, optical diodes, and multi-mode or single-mode fibers. 10GBase-LX4 will play an important role in the Ethernet in the near future.
In this thesis, first we design a deserializer for 10GBase-LX4 receiver. The deserialzier functions as a data type converter. As a high-speed data stream came from Clock/Data Recovery is input, the deserializer not only achieves byte-level synchronization by detecting the alignment character, but it also converts the high-speed input stream into lower-speed parallel output.
Subjects
序列-並列轉換器
電流模式邏輯電路
10GBase-LX4乙太網路
8B/10B編碼
Deserializer
Current-Mode Logic
10GBase-LX4 Ethernet
8B/10B Code
Type
thesis