Power-Aware Motion Estimation Processors for Mobile Video Applications
Date Issued
2004
Date
2004
Author(s)
Lin, Siou-Shen
DOI
zh-TW
Abstract
Motion estimation is the fundamental technique of video coding, which effectively reduces the temporal redundancy among video sequences, and it is widely used in nowadays video compression standards. However, it takes huge amount of computation to perform the motion estimation, which makes the battery-powered mobile video application difficult. In this thesis, two solutions are proposed for
the high-end mobile video device and the power-aware mobile video system respectively.
For the high-end mobile video device, the low-power full search motion estimation processor is developed. In this section, a novel low-power parallel tree architecture is proposed for the full search block-matching motion estimation. The parallel tree architecture exploits the spatial data correlations between parallel candidate block searches for data sharing, which effectively eliminates huge
amount of data access bandwidth while consumes fewer hardware resources compared with array-based architectures. Combining with adaptive parallel partial distortion elimination algorithm, the required average clock cycle count for each macroblock search can be greatly reduced to below 50% to achieve low-power operation. Besides, this architecture can also eliminate redundant computation
without pipeline latency and excess power consumption caused by register data shifting and redundant memory accessing in array-based architectures. In chip implementation, the power consumption is 13.5 mW at 20MHz and 1.35V under the UMC 0.18 µm CMOS 1P6M process with 667K transistor counts. The proposed chip is suitable for high-end real-time mobile video encoding system, which desires high-quality video but low power consumption.
For the power-aware mobile system, the multi-mode power-aware reconfigurable motion estimation processor is implemented. In the algorithm level, by exploiting the characteristics of video signal, two content-aware decision criteria are proposed to identify the complexity of motion vectors. Based on these two decision criteria as well as different combinations of motion estimation algorithms,
four different modes are proposed to vary the computation resources under different power constraints dynamically. Besides, the proposed decision criteria also enable the maximization of quality under each power constraint by quality-driven diversity-based search approach. In the architecture level, by analyzing the similarity between different motion estimation algorithms, the power-aware
reconfigurable motion estimation architecture, which can switch different algorithm in real-time requirement easily, is proposed with small hardware overhead. The processor is fabricated under the UMC 0.18 µm CMOS 1P6M process with
546K transistor counts. According to our simulation results, the post-layout gate-level power consumptions are 51.27 mW, 24.88 mW, 13.76 mW , and 8.46 mW for each mode respectively, and with only 0dB, 0.0036dB, 0.01dB, and 0.16dB average quality degradation. Therefore, the proposed processor is well-suited for mobile video coding systems that desire power-awareness feature.
Subjects
移動估計
行動視訊
功率感知
Power-Aware
Motion Estimation
Mobile
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-93-R91943081-1.pdf
Size
23.31 KB
Format
Adobe PDF
Checksum
(MD5):79ee9abe961957b4990e1b75ce3a06bd