Miniature 3-D inductors in standard CMOS process
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
37
Journal Issue
4
Pages
471-480
Date Issued
2002-04
Author(s)
Abstract
The structure of a miniature three-dimensional (3-D) inductor is presented in this paper. The proposed miniature 3-D inductors have been fabricated in a standard digital 0.35-/spl mu/m one-poly-four-metal (1P4M) CMOS process. According to the measurement results, the self-resonance frequency f/sub SR/ of the proposed miniature 3-D inductor is 34% higher than the conventional stacked inductor. Moreover, the inductor occupies only 16% of the area of the conventional planar spiral inductor with the same inductance and maximum quality factor Q/sub max/. A 2.4-GHz CMOS low-noise amplifier (LNA), which utilized the proposed miniature 3-D inductors, has also been fabricated. By virtue of the small area of the inductor, the size and cost of the radio frequency (RF) chip can be significantly reduced.
SDGs
Type
journal article