Design of clustering analyzer based on systolic array architecture
Resource
Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on
Journal
Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on
Pages
-
Date Issued
1994-12
Date
1994-12
Author(s)
Lai, Mao-Fu
Wu, Yan-Pei
Hsieh, Chaur-Heh
DOI
N/A
Abstract
This paper presents a systolic architecture for the squared-error clustering algorithm. The proposed architecture exploits a 2-dimensional systolic array which uses intensively parallel and pipelined processing. The architecture dramatically reduces the huge number of processing elements required by previous architectures. Furthermore, the same organization can be utilized for applications where the number of input patterns is varied. In addition, the time complexity of our architecture is reduced in comparison with earlier architectures. A cost-effective VLSI implementation for high speed clustering analysis can be realized with considerably less circuit complexity using this novel architecture.
Type
journal article
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