Architecture design of high performance embedded compression for high definition video coding
Journal
2008 IEEE International Conference on Multimedia and Expo, ICME 2008
Pages
825-828
Date Issued
2008
Author(s)
Abstract
External memory bandwidth is an important issue in System-on-Chip (SoC) systems. Especially in high definition (HD) video coding, the bandwidth requirement of off-chip memory is critical in video processing. In recent researches, embedded compression shows high potential on off-chip memory bandwidth reduction. Works about embedded compression have been done for low power applications. However, there is no suitable efficient embedded compression with good rate-distortion performance for high throughput applications. In this paper, an algorithm and hardware architecture of high performance lossy embedded compression is proposed to ease the bus congestion problem while keeping the latency low. Using the proposed algorithm, not only the high throughput requirement of HD video encoder is met, but also the hardware cost is relatively low. From our simulation, about 70% memory bandwidth is reduced with only 0.1dB PSNR degradation in 1080p HD video.1 © 2008 IEEE.
Subjects
Embedded compression; Motion estimation; Video coding
SDGs
Other Subjects
Application specific integrated circuits; Bandwidth; Boolean functions; Data compression; Data storage equipment; Exhibitions; High performance liquid chromatography; Image coding; Integrated circuits; Motion estimation; Programmable logic controllers; Programming theory; Telecommunication systems; Throughput; Traffic congestion; Visual communication; Applications.; Architecture designs; Bandwidth requirements; Chip memories; Chip memory bandwidths; Congestion problems; Efficient; Embedded compression; Embedded compressions; External memories; Hardware architectures; Hardware costs; HD videos; High definition videos; High definitions; High potentials; High throughputs; High-performance; Low power applications; Memory bandwidths; PSNR degradations; Rate-distortion; System-on-chip; Video coding; Video processing; Bandwidth compression
Type
conference paper