The Design and Implementation of High-Speed Wireline Transceivers in CMOS Technology
Date Issued
2008
Date
2008
Author(s)
Chen, Ming-Shuan
Abstract
A full study of three data formats including duobinary, PAM4, and NRZ is proposed to estimate the performance of the corresponding transceivers under different conditions. Transceiver prototypes designed and optimized for the three signalings are presented to evaluate their feasibility and to validate the performance prediction. The three transceivers have been tested thoroughly in Rogers and FR4 boards. Fabricated in 90-nm CMOS technology, all three transceivers achieve error-free operation with 20-Gb/s 231 − 1 PRBS data over 40-cm Rogers and 10-cm FR4 channels.nother one low-power high-speed I/O interfaced circuit targeting for data transmission between timing controller and column driver in TFT-LCD panel is proposed. The circuit uses a signal with very low amplitude and a high-speed transimpedance amplifier to reduce the power consumption while operating at a high data rate. The circuit is designed and fabricated in TSMC 0.35um CMOS technology. It can achieve error-free operation with 1.2-Gb/s 231-1 PRBS data over 55-cm FR4 channels. The power consumption is 4 mW under 3.3V supply and the core area is 0.1mm2.
Subjects
Backplane transceiver
wireline transceiver
duobinary
pam4
NRZ
Type
thesis
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