TARGET：Timing-AwaRe Gate Exhaustive Transition Fault Simulation and Test Pattern Selection for Cell-internal Defects
Date Issued
2014
Date
2014
Author(s)
Lin, Ang-Feng
Abstract
In advanced technology, cell-internal defects gain more attention than before. Those well-known fault models all assume defects are between standard library cells. Besides, accurate metric is needed for modeling small delay defects and internal defects. Some cell-internal defects can be modeled as small delay faults. This thesis presents a timing-aware gate exhaustive transition fault (TARGET) fault simulation and test pattern selection for cell-internal defects. Our TARGET test patterns combine both the benefits of cell-aware and timing-aware ATPG. It tries to launch gate output transitions from as many different gate input transitions as possible. We proposed TARGET coverage and TARGET SDQL to evaluate the quality of our test patterns. TARGET does not require exhaustive SPICE simulation to characterize each library cell. Compared with traditional $N$-detect and timing-aware test patterns, the proposed TARGET test patterns have better TARGET coverage given the same test length.
Subjects
測試向量自動生產器
邏輯閘內部缺陷
邏輯閘窮舉轉態
Type
thesis
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