Sensitivity-based multiple-Vt cell swapping for leakage power reduction
Journal
2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Pages
168-171
Date Issued
2008
Author(s)
Abstract
With the technology advancement, leakage power has become a significant source of total power consumption, and thus it is desirable to develop effective leakage-power reduction techniques for power optimization. The sensitivity-based technique has been shown to be an efficient approach to leakage power reduction by swapping gates (cells) with different threshold voltages. Nevertheless, its solution quality is limited and unstable because the technique does not have a global view on the effects of the gate swapping on other gates. To remedy this weakness, we develop a novel sensitivity formulation with a more global view on the gate-swapping effects. We also develop two static-timing-analysis engines embedded in the proposed algorithm to improve the efficiency. Experimental results show that our algorithm can effectively reduce leakage power by up to 74.4%. Compared with the state-of-the-art sensitivity-based method, we can achieve more leakage-power reduction by up to 20.6% and consume less running time and memory. The results show the effectiveness and efficiency of our algorithm. ©2008 IEEE.
SDGs
Type
conference paper