A novel current model for CMOS gates
Resource
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Journal
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Pages
-
Date Issued
1992-05
Date
1992-05
Author(s)
Wang, Jyh Herng
Fan, Jeng Ten
Feng, Wu Shiung
DOI
N/A
Abstract
Accurate current analysis is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drops, etc. A new current model for CMOS gates is presented in this paper. The current waveform of a CMOS gate can be divided into three regions and the characteristics in each region can be approximated by an exponential function. After analyzing the possible transition of a gate, the current waveform under one input vector can be obtained with only four parameters. This model can be used in any switch-level timing simulators to generate the current waveforms after the voltage waveforms are obtained. The simulated current waveform, instead of the average estimation, helps solving the VLSI reliability problems due to the electromigration and excess voltage drops in the power buses. When comparing the results obtained by using SPICE and our model, we can find the agreement, especially the time points that current pulses happen.
Type
journal article
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