Investigation of Current Tunneling Behavior for p- and n-type MOS Capacitors with Ultra-thin Oxides
Date Issued
2014
Date
2014
Author(s)
Lu, Han-Wei
Abstract
In this thesis, the current tunneling behaviors of MOS(p) and MOS(n) capacitors with ultra-thin SiO2 dielectric were explored under both accumulation and deep depletion modes. In Chapter 2, it is found that there is a clear “kinked point” in every I-V curve of MOS(p) capacitor under accumulation mode. It is reasonable to suspect that it is related to the unsymmetrical structure between the metal aluminum and substrate Si. By the theoretical simulation with the experimental results, it is concluded that the kinked voltage VG@|JG|’min is inferred to VG@EFS=EV but not VFB and are strongly dependent on oxide thickness, Dit, and Qeff/q. Based on the intrinsic kinked characteristic of I-V curve under accumulation region in MOS(p) devices, a further application to extract ultra-thin oxide thickness will be carried out. On the other hand, this kinked phenomenon does not appear in the forward positive bias J-V curve of MOS(n) capacitors. That is because there is no change of the direction of the band bending for MOS(n) capacitors in the forward bias. In Chapter 3, it is found that the dependencies of I-V curves on gate oxide thickness for MOS(p) and MOS(n) capacitors are definitely different. Interesting area- and perimeter-dependent mechanisms of gate current are observed. The main issue is the Schottky barrier between metal and the silicon substrate could not be ignored for MOS(p) capacitors but would be less pronounced for MOS(n) capacitors. In addition, the effect of fringing field would further enhance the edge-dependent current conduction of MOS(p) capacitors. For MOS(n) capacitors, the current are area-dependent. In Chapter 4, to study this lateral non-uniformity phenomenon, three different thicknesses of top aluminum gate are intentionally designed to MOS(p) capacitors. According to C-V and I-V measurements carried out in the dark, it is found that the device with thin (< 4 nm) top Al-gate will result in entirely different electrical characteristics compared with the device with thick top Al-gate. It shows that the area beneath the probe enters deep depletion region earlier. And other areas which are still in inversion region will provide electrons to the gate center and therefore induce extra current in deep depletion region. That is, there is enhanced edge charge collection efficiency in inversion due to edge fringing field effect. Through this study, a thorough understanding of the basic characteristics of MOS(p) and MOS(n) capacitors could be achieved.
Subjects
current tunneling behavior
kinked effect
area/perimeter dependencies
MOS capacitors
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-103-F97943064-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):c72e18af247a48fe6fca368d12da0c2a