A high frequency power and area efficienct charge-pump-constant-on-time controlled DC-DC converter based on dynamic-biased comparator with 50mV droop and 2us 1% settling time for 1.15A/1ns load step
Journal
Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
Journal Volume
2019-March
Pages
2980-2983
Date Issued
2019
Author(s)
Abstract
This paper presents a novel constant-on-time controlled buck converter IC with charge-pump-synthesized-ripple for compensation. The proposed technique replaces the external ramp generator by a simple charge-pump circuit to alleviate the sub-harmonic instability problem of ripple-based constant-on-time (RBCOT) control. Moreover, it can effectively minimize the size of on-chip resistor and capacitor compared with VIC-based COT. Without using any wide bandwidth analog processing circuitry, this new control scheme achieves small cost of power and area simultaneously under high switching frequency operation. The conventional on-time generator operating at high switching frequency needs a high speed comparator which consumes huge current. To solve this issue, a quadratic bias current reusing on time ramp information is adopted in the modified dynamic-biased comparator. Thus, the average current consumption of comparator is reduced by 58% compared with the traditional constant-biased method in CCM. The circuit is implemented in a 0.18um CMOS process with near 10MHz high switching frequency. For the 1.15A/1ns load step, the simulation result shows near time-optimal transient response with only 50mV droop and 2us 1% settling time. ? 2019 IEEE.
Subjects
Charge pump circuits; Comparator circuits; Comparators (optical); Electric inverters; Power electronics; Transient analysis; Analog processing; Average currents; Control schemes; High frequency power; High speed comparator; High switching frequencies; On-chip resistors; On-time controls; DC-DC converters
Type
conference paper