Power-aware hardware/software partitioning for embedded systems
Date Issued
2007
Date
2007
Author(s)
Liao, Wei-Yi
DOI
zh-TW
Abstract
In this paper, we present a power-aware partitioning approach for a class of embedded systems that are modeled by program graphs. The goal of approach is to find the most
appropriate partition to minimize the considered energy consumption as well as the execution time of the system. The main concept of the approach is the critical software
parts are accelerated on hardware to reduce the total system energy. The proposed approach is based on the estimation of energy consumption of hardware and software
blocks and a heuristic rule to determine the feasible partition. In addition to the software and hardware parts, we also take into the required communication between
the hardware and software blocks of a partition. A embedded system composed of soft cores and coarse-grain reconfigurable hardware is considered and implemented on an
FPGA, platform called DE2.
We use the Altera SOPC Builder to build systems and evaluate embedded systems and employ the PowerPlay Power Analyzer tool to estimate system energy consumption.
As compared to all-software implementation, the hardware/software partitioning results show that we can obtain up to 91.96% speedups, and up to 28.15% energy savings. The quality of the proposed partitioning approach is also testified by the high accuracy rate of 93.88% when comparing estimated results with experiment result.
Subjects
軟硬體分割
軟核
FPGA
電源消耗量
電源估計
Hardware/software partitioning
soft core processor
energy estimation
SDGs
Type
thesis
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