Electrical characterization of 4H-SiC metal-oxide-semiconductor structure with Al2O3 stacking layers as dielectric
Journal
Applied Physics A
Journal Volume
124
Journal Issue
2
Pages
337-351
Date Issued
2018
Author(s)
P.K.Chang
Abstract
Interface defects and oxide bulk traps conventionally play important roles in the electrical performance of SiC MOS device. Introducing the Al2O3 stack grown by repeated anodization of Al films can notably lower the leakage current in comparison to the SiO2 structure, and enhance the minority carrier response at low frequency when the number of Al2O3 layers increase. In addition, the interface quality is not deteriorated by the stacking of Al2O3 layers because the stacked Al2O3 structure grown by anodization possesses good uniformity. In this work, the capacitance equivalent thickness (CET) of stacking Al2O3 will be up to 19.5 nm and the oxidation process can be carried out at room temperature. For the Al2O3 gate stack with CET 19.5 nm on n-SiC substrate, the leakage current at 2 V is 2.76 × 10−10 A/cm2, the interface trap density at the flatband voltage is 3.01 × 1011 eV−1 cm−2, and the effective breakdown field is 11.8 MV/cm. Frequency dispersion and breakdown characteristics may thus be improved as a result of the reduction in trap density. The Al2O3 stacking layers are capable of maintaining the leakage current as low as possible even after constant voltage stress test, which will further ameliorate reliability characteristics. © 2018, Springer-Verlag GmbH Germany, part of Springer Nature.
Other Subjects
Capacitance; Interfaces (materials); Leakage currents; Silica; Silicon carbide; Wide band gap semiconductors; Breakdown characteristics; Capacitance-equivalent thickness; Constant voltage stress tests; Electrical characterization; Electrical performance; Interface trap density; Reliability characteristics; Semiconductor structure; Silicon compounds
Type
journal article