Low-voltage BiCMOS four-quadrant multiplier and squarer
Journal
Journal of Analog Integrated Circuits and Signal Processing
Journal Volume
20
Journal Issue
1
Pages
25-29
Date Issued
1999-07
Author(s)
Abstract
A new low-voltage low-power BiCMOS four-quadrant multiplier using cascade NPN and NMOS pairs is presented. This circuit has been fabricated in a 1 μm BiCMOS process. Experimental results show that for a power supply of ±1.5 V, the linear range is over ±0.8 V with the linearity error less than 2%. The total harmonic distortion is less than 2% with input range up to ±0.8 V. The measured -3 dB bandwidth of the proposed multiplier is about 10 MHz. Its static power dissipation is about 50 μW. The squarer modified from the proposed multiplier has the input range up to ±1 V. This circuit is expected to be useful in low-voltage analog signal processing applications.
SDGs
Type
journal article