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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
Multiple chip planning for chip-interposer codesign
Details
Multiple chip planning for chip-interposer codesign
Journal
Design Automation Conference
Date Issued
2013
Author(s)
Ho, Y.-K.
YAO-WEN CHANG
DOI
10.1145/2463209.2488767
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-84879875838&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/380153
SDGs
[SDGs]SDG9
Type
conference paper