A 75-GHz phase-locked loop in 90-nm CMOS technology
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
43
Journal Issue
6
Pages
1414-1426
Date Issued
2008
Author(s)
Abstract
The design and experimental verification of a 75-GHz phase-locked loop (PLL) fabricated in 90-nm CMOS technology is presented. The circuit incorporates a three-quarter wavelength oscillator to achieve high-frequency operation and a novel phase-frequency detector (PFD) based on SSB mixers to suppress the reference feedthrough. The PLL demonstrates an operation range of 320 MHz and reference sidebands of less than -72 dBc while consuming 88 mW from a 1.45-V supply. © 2008 IEEE.
SDGs
Type
journal article