Study on a Generic Decoder Architecture for Irregular LDPC codes
Date Issued
2005
Date
2005
Author(s)
Lin, Hsiu-Min
DOI
zh-TW
Abstract
In this paper, we propose a reconfigurable decoder architecture suitable for generic irregular LDPC (Low Density Parity Check) decoding. First of all, we study LDPC property in detail. Secondly, we survey the LDPC various decoding algorithms and propose an architecture that implements the decoding algorithm with reconfigurability according to standard or specification which adopt LDPC as the channel code, such as IEEE 802.11n proposals, IEEE 802.16d and IEEE 802.3an. The architecture is a broadcast-based architecture with Content Address Memory (CAM) that can decode various kinds of parity check matrices. Finally, the decoder has been verified in C and RTL code for three different parity check matrices. FPGA prototyping is also conducted and successfully tested for a case with smaller parity check matrix due to the limitation in the FPGA device. After normal verification and FPGA measurement, our architecture has been demonstrated to decode efficiently.
Subjects
低密度奇偶檢查碼
內容位址記憶體
廣播式
通用型
LDPC
Low Density Parity Check
CAM
Broadcast
irregular
Generic
SDGs
Type
thesis
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