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  4. Algorithm and Hardware Architecture Design of Perception-Aware Motion Compensated Frame Rate Up-Conversion
 
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Algorithm and Hardware Architecture Design of Perception-Aware Motion Compensated Frame Rate Up-Conversion

Date Issued
2010
Date
2010
Author(s)
Wang, Ya-Ting
URI
http://ntur.lib.ntu.edu.tw//handle/246246/257029
Abstract
Frame rate up-conversion (FRUC) is a technique converting video sequence from lower frame rate to a higher one, which is originally widely-used in the video compression system to reconstruct frames at the decoder side that skipped by the encoder, and also applied in the high frame rate LCD system nowadays to reduce motion artifacts. Among the motion blur reduction methods, motion-compensated frame interpolation (MCFI) yields the best interpolation results by taking the motion information into consideration and no decrease in the overall brightness. However, the cost is high, since the process to estimate and compensate motions in the MCFI algorithm is computationally expensive, and with high bandwidth and memory requirements. The target application of this work is the HDTV system using LCD with 120Hz refresh rate, where a cost-effective MCFI hardware is desirable for such system, and the frame rate that is much higher than the sampling rate of human eye motivated us to seek cost reduction solution with the perceptual characteristics of human eye. In this thesis, a psychophysical experiment has been conducted and the capability of human to distinct the difference between the motions displayed with 60fps and 120fps is studied. Where the difference of motions with velocity under 3 °/sec and with duration under 100 ms in 60fps and 120fps has proved to be hard-to-detective for human eyes. Base on the psychophysical experiment results, a novel hardware-oriented perception-aware motion-compensated frame interpolation algorithm is proposed. For the VLSI hardware design, the target specification is set to 1920x1080 frame size, with throughput of 60 interpolated frames per second. The hardware is implemented with Verilog-HDL and synthesized with SYNOPSYS Design Compiler. Faraday 90um cell library is adopted to design the hardware. The total gate count is 212K.
Subjects
Frame Rate Up-Conversion
Perception
Motion-Compensated
Bilateral Motion Estimation
Type
thesis
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