Algorithms and Architectures of QC-LDPC Decoder Designs for Advanced Communication Systems
Date Issued
2010
Date
2010
Author(s)
Shih, Xin-Yu
Abstract
Low-Density Parity-Check (LDPC) Codes are one kind of channel coding schemes. They were first introduced by Gallager in 1962, and verified to own the best error-correcting capabilities. After three decades, LDPC Codes were rediscovered by Dr. MacKay. As the advanced VLSI technology proceeds, the interests in LDPC Codes have been dramatically increased because of their excellent error-correcting performance. Even the decoding performance of LDPC Codes is much better than that of Turbo Codes. It becomes feasible to implement LDPC Codes as the kernel Forward Error Correction (FEC) module in the modern advanced communication systems. Hence, for different circuit design considerations, we develop three LDPC decoder chips with measurement results in the hardware architecture level. Besides, in the algorithm level, we also propose a universal matrix-merging algorithm for accommodating multi-mode design.
1) A high-performance cost-effective (1944, 972) LDPC decoder chip for IEEE 802.11n system: In order to achieve high-performance cost-effective characteristic, Efficient Checkerboard Layout Scheme (ECLS) is proposed for the back-end chip design. Also, it is developed with three design techniques, such as Two-Stage Group Comparison (TSGC), Flexible Wordlength Assignment (FWA), and Data Packet Scheme (DPS). The chip in TSMC 0.13um CMOS technology can be measured at 111.1 MHz with 76 mW. It features low area cost, low power dissipation, critical path shortening, decoding performance improvement, and throughput enhancement.
2) A 19-mode LDPC decoder chip for IEEE 802.16e system: We propose the multi-mode hardware architecture of the LDPC decoder design. Besides, we also develop three design techniques, including Base-Matrix Reordering (BMR), CNU/BNU Overlapped Operations (CBOO), and Soft-Decision Early Termination Scheme (SD-ETS). Via TSMC 0.13um CMOS technology, the chip is measured at 83.3 MHz with 52 mW. Its benefits are smaller chip area, higher hardware utilization, lower decoding latency, flexible decoding throughput, and lower power consumption.
3) A run-time reconfigurable multi-rate LDPC decoder chip for next-generation channel-adaptive communication system: The run-time reconfigurable hardware architecture is proposed for the users to run-time download the desired parity check matrix. In addition, three developed design techniques are Divided-Group Comparison (DGC), Dynamic Wordlength Assignment (DWA), and Channel-Adaptive Early Termination Scheme (CA-ETS). Based on ECLS, Matrix-Like Memory Layout Placement (ML-MLP) is proposed to enhance core utilization and reduce power/energy consumption. In the ASIC chip implementation, by using TSMC 0.13um CMOS technology, the maximum frequency operates at 125 MHz and the power dissipates 58 mW in average. It can deliver run-time reconfigurable property, critical-path shortening, decoding performance improvement, decoding latency saving, small chip area, and low power/energy consumption.
4) A universal matrix-merging algorithm for accommodating multi-mode design with very different parity check matrices: It is used to efficiently reduce wiring complexity of a multi-mode LDPC decoder design. Among very different parity check matrices, we can find out the optimal solutions to minimize the hardware overhead with respect to a single-mode design. Additionally, we would use three different parity check matrices with code rate of 1/2 defined in IEEE 802.11n system for demonstrating the design examples with its benefits.
In summary, for various design considerations in the modern advanced communication applications, the proposed algorithms and architectures of the LDPC decoder designs are verified with demonstrated design examples in this dissertation.
Subjects
LDPC Codes
SDGs
Type
thesis
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