On the Switching Loss of the SiC MOSFET Parasitic Capacitors
Journal
WiPDA Asia 2023 - IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia
ISBN
9798350337112
Date Issued
2023-01-01
Author(s)
Ho, Tzu Hsuan
Abstract
A study of the parasitic capacitor losses of SiC MOSFETs during the switching transient is presented in this paper. It is well-known that the capacitance of the parasitic capacitor of the SiC MOSFET is highly affected by its drain-source voltage. Therefore, the calculation of power loss during the switching transient is highly affected by the nonlinear capacitance variation. On the other hand, the parasitic capacitor loss exists during the no-load condition, so it is necessary to separate the parasitic capacitor power loss from the on-resistor conduction loss of the power switch. In this paper, the switching loss caused by the parasitic capacitor is discussed and analyzed. The Coss-Vds characteristic curve with the linear regression progress will be utilized to calculate the power loss during the switching transient. A hardware measurements obtained from a half-bridge SiC MOSFET module will be used to evaluate the power loss calculation during the switching transient. Based on the analyses obtained from this paper, a simplified approach to determine the approximated power losses caused by the parasitic capacitors can be expected.
Subjects
parasitic capacitance | SiC MOSFET | switching loss estimation
SDGs
Type
conference paper