Design and Implementation of CMOS Gb/s FSK Transceiver for 60 GHz Indoor Wireless Communications
Date Issued
2007
Date
2007
Author(s)
Wen, Sung-Han
DOI
en-US
Abstract
The contiguous bandwidth of 7GHz around 60GHz enables the realization of the ultra high-speed indoor wireless communications. In the recent years, many critical circuits at 60GHz have been fabricated in the CMOS technology to demonstrate the possibility of the low cost transceiver implementation. In addition to the front-end circuit and the frequency synthesizer, the ultra high-speed modulator and demodulator are also of main concern in 60-GHz systems. This thesis presents a 60-GHz frequency divider and a Gb/s FSK transceiver for 60 GHz indoor wireless communications.
A 60-GHz injection-locked frequency divider is implemented in a 0.13-μm CMOS technology. Compared with the shunt-peaking version, the proposed power-matched technique improves the locking range by 15% based on the simulation results. The measurement results show that the free-running frequency of the divider is 30.4GHz and the total locking range is 6GHz (10%) at input power of 3dBm while consuming 8.8mW from a 1.2V power supply.
The proposed mixer-based BFSK transmitter with injection locking technique achieves both 1Gbps operation speed and good out-band spur reduction. Measured settling time and spur reduction gain of the transmitter are 380ps and 8dB respectively while consuming 51mW from a 1.8V power supply. This transmitter is fabricated in a 0.13-μm CMOS technology.
A Gb/s FSK receiver is realized in a 0.13-μm CMOS technology. In Comparison with the LC-tank delay cell, the proposed injection-locked cell solves the critical delay-control problem of the conventional quadrature demodulator. The simulated demodulation constant of the receiver is 424mV/GHz while consuming 21mW from a 1.2V power supply.
Subjects
注入鎖定振盪器
可適性突波壓制技術
注入鎖定單元
injection-locked oscillator
adaptive spur reduction technique
injection-locked cell
Type
thesis
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