Direct synthesis of hazard-free asynchronous circuits from STGs based on lock relation and MG-decomposition approach
Resource
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Journal
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design
Pages
Proceeding-s
Date Issued
1994-03
Date
1994-03
Author(s)
Lin, Kuan-Jen
Kuo, Jih-Wen
Lin, Chen-Shang
DOI
N/A
Abstract
A new realization algorithm is proposed to synthesize asynchronous hazard-free circuits directly from signal transition graphs (STGs) with underlying free-choice Petri nets. Based on a signal lock relation and MG-decomposition approach, the synthesis method does not use state diagrams and thereby maintains problem size polynomially proportional only to the number of signals. Moreover, the synthesized circuits are guaranteed to be hazard-free under unbounded gate-delay mode without any post-realization analysis and modification. A sufficient condition for hazard-free realization is also derived based on the signal lock relation in STGs. The high-levelness of this condition allows easier manipulation of the specification for realizability. The proposed direct-synthesis algorithm has been shown successful on over thirty academic and industrial examples.
Type
journal article
File(s)![Thumbnail Image]()
Loading...
Name
00326879.pdf
Size
663.02 KB
Format
Adobe PDF
Checksum
(MD5):f4dc3bf9ef93cc40dc71ad053f7b60fb