Scalable low-complexity digit-serial VLSI architecture for RSA cryptosystem

Journal

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Pages

586-595

Date Issued

1999

Author(s)

AN-YEU(ANDY) WU

Leu, Jye-Jong

AN-YEU(ANDY) WU

URI

http://www.scopus.com/inward/record.url?eid=2-s2.0-0033343160&partnerID=MN8TOARS

http://scholars.lib.ntu.edu.tw/handle/123456789/350721

Type

journal article