A Class D Audio Amplifier using Loop Filter and Driver Delay Hysteresis Control
Date Issued
2010
Date
2010
Author(s)
Chiu, Hang-Quei
Abstract
A simple circuit implementation of hysteresis controlled class D amplifier(CDA) is proposed in the thesis. Since the proposed circuit puts additional delay before the gate driver and switching stage in CDA to realize the hysteresis control, new control method is called driver delay hysteresiscontrol(DDHC).
In this thesis, we analyse the total harmonic distortion(THD) and power supply rejection ratio(PSRR) of the proposed DDHC CDA. The analytical expression shows that the distortion source in the common hysteresis control(bang-bang control) CDA is completely dismissed in the DDHC CDA.
The measurement results show that the proposed DDHC CDA has lower THD compared to PWM CDA in whole audio band. The proposed DDHC CDA is integrated and fabricated in 3.3V 0.35μm 2P4M CMOS process with 0.53x0.4 mm^2 active layout area. The measurement results show the THD+N ratio is flat and below 0.03% between 20Hz and 20kHz and PSRR is 64dB for a -30dBV,217Hz standard GSM perturbation noise. The measured SNR is 80dB at -60dB from full scale. The power efficiency is 80% at full power.
Subjects
class D
hysteresis control
THD
loop filter
Type
thesis
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